Appendix A Comparison with the AXI4 Write Data Channel Read this for a description of the key differences between the AXI4-Stream interface and the AXI4 write data channel. One major up-dation seen in AXI is that, it includes information on the use of default signaling andSupports multiple outstanding transactions: * Supports connected masters with multiple reordering depth (ID threads). What is the difference between burst and beat? A ‘beat’ is an individual data transfer within an AXI burst. 2. Google Docs Spreadsheet Insert Text Box. Write data interleave happen when two AXI bus masters generate sequence of write data to the same slave, but the write data doesn't arrive every clock cycle. Share this document with a friend. . Set slave and controller specific parameters. In AXI4 we don't have write data interleaving, so if your master is issuing multiple write transactions using different IDs, there is a strict ordering requirement that all the WDATA transfers for the first issued AW channel transfer must be completed before any of the WDATA transfers for the second issued AW channel transfer. INTRODUCTION The NIC-400 is the 4th generation AXI interconnect from ARM and is delivered as a base product of AMBA. Migrating from AHB to AXI based SoC Designs This article describes the most important AMBA bus architectures and how they evolved to accommodate to the ever increasing complexity of SoC technology. メモリインターリーブ（英：memory interleaving）とは、 主記憶装置（メインメモリ）へのアクセスを高速化 する手法のひとつです。. • AXI Protocol Converter connects one AXI4, AXI3 or AXI4-Lite master to one AXI slave of a different AXI memory-mapped protocol. By disabling cookies, some features of the site will not workSometimes I need to verify a write-only AXI interface, such as in this AXI-lite write-channel to wishbone bridge. But it's not the only possible source of interleaved write data. This is to simplify the address decoding in the interconnect. AXI3 supports write interleaving. 4. axi_crossbar module. 3. I have a few fundamental questions related to AXI-4 and I would appreciate if anyone can answer these. In the AXI protocol, can you help me understand in depth about the multiple outstanding addresses, out-of order completion and data interleaving Scenario 1: There is Only 1 AXI master (with support of only 1 Master ID) doing transaction to a slave which is capable of handling multiple outstanding addresses. Re-ordering implies the transactions complete in a different order to that the AR channel transfers were completed, whereas interleaving suggests that more that one read data stream can be active, so data in successive transfers could be for different transactions. • uses burst-based transactions with only the start address issued. svt_axi_checker:: snoop_transaction_order_check. Embed Size (px. The addressing phase is similar to a read. AXI is basically a multi-layer (i. I have and watch many IP providers e. Read online or download PDF • Page 696 / 783 • Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual • Altera Measuring instrumentsInterleaved DMA: Interleaved DMA are those DMA that read from one memory address and write from another memory address. 0 data and address widths; Supports all protocol transfer types, burst types, burst lengths and response types; Supports constrained randomization of protocol attributes. compatibility of interface parameters such as write interleaving and acceptance depths, bus widths, ID widths etc. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. 0. " 1. . 是否支持乱序只与slave有关，与master无关。. The data widths supported are: 32, 64, 128, 256, 512 and 1024. >or its possible with single-master cases also? Yes. * Multi-threaded traffic (masters issuing multiple ID threads) is supported across the interconnect topology regardless of internal. 1A is a view illustrating a process of interleaving the data transmitted by plural AXI masters and transmitting the interleaved data to an AXI slave 30 having interleaving acceptance capability of “2”. pdf". 4x, and energy efficiency. In this case, the arbiter seems like compulsory for all the readback data coming from different slave & the arbiter to determine which readback data that has higher priority can or through round-robin way to return to the master. The higher bits can be used to obtain data from the module. With the new AXI4-Stream protocol (see below), write interleaving is still available. SIZE 2. ° Write interleaving: This feature was retracted by AXI4 protocol. Recently, I read "AMBA AXI Protocol. For each of the AXI channels the flow of information is one direction, so for the AW, AR and W channels the flow is master to slave, and for R and B the flow is slave to master. This site uses cookies to store information on your computer. A single instance of the AXI NoC IP can be configured to include one, two, or four instances of the integrated MC. This site uses cookies to store information on your computer. awvalid { Write address valid, indicates that valid write address and control information are available. Write buffer between stage 1 and 2 to store interleaving write packets Parameters of AXI4[-Stream] protocol can be adjusted in AXI4. This document gives explanation about Cortex-A9 AXI masters. While AXI 4 only supports read data interleave. AXI4 supports QoS, AXI3 does NOT support QoS. Introduction. A master places an address on the AWADDR line and asserts a valid signal. This specification defines the AMBA AXI-Stream protocols: • AXI4-Stream • AXI5-Stream The collective term AXI-Stream is used in instances that describes common features. close to full bandwidth in the interleaved output stream, and maybe also in one of the input-streams, assuming the rest are slow), then we need to FIFO-buffer data corresponding to at least the size of one arbitration-block on each of the switch. AXI-4 questions. Separate address/control, data and response phases. , Simon Fraser University, 2010. beat_num - Indicates the beat number for which the byte count is to be calculated. AXI4 does NOT support write interleaving. AXI4 supports QoS, AXI3 does NOT suppor QoS. parameter [0: 0] F_OPT_NO_READS = 1'b0, F_OPT_NO_WRITES is the. amba 3. ° Supports write response re-ordering, Read data re-ordering, and Read Data interleaving. Since AXI has 5 parallel channels running, many wires are used to lay the layout. IF write or read reordering depth is 4, does this mean that the transaction coming with ARIDs for ex 3, 2, 1, 0 can be re ordered and give response for 0,1,2,3 write and read interleaving and reordering depths. 2'b00 prefixes a read request, 2'b01 a write request, 2'b10 a set address request, and 2'b11 is either a reset request (handled earlier) or a. atomic access, narrow transfer. attribute type static const string, defined in class svt_err_check_stats_cov_exokay_not_sent_until_successful_exclusive_store_rack_observed_check: type_name{"payload":{"allShortcutsEnabled":false,"fileTree":{"src":{"items":[{"name":"axi_atop_filter. In write transactions, in which all the data flows from the master to the slave, the AXI protocol has an additional write response channel to allow the slave to signal to the master the completion of the write transaction. although me have twos questions info AXI according hi. 文章浏览阅读2. Low-power Interface support; Atomic access support with normal access,exclusive access and locked access; AXI4 supportsvt_axi_system_transaction:: master_xact. but i have two questions about AXI afterPrefix A Denotes global Advanced eXtensible Interface (AXI) signals: Prefix AR Denotes AXI read address channel signals. Write interleave capability 1 No write interleaving is performed. . In AXI Interconnect IP configuration, I changed the Acceptance parameter to 5 from 1 (All sides : Master Read/Write, Slave Read/Write). The Advanced eXtensible Interface ( AXI) is an on-chip communication bus protocol and is part of the Advanced Microcontroller Bus Architecture specification (AMBA). 0 AXI. but i have two questions about AXI after hi. AMBA AXI and ACE Protocol Specification Version E. but i saw AMBA 3. 标准化：配套提供标准模型和检查器以供设计人员使用。. sv","contentType":"file"},{"name":"axi. Select PS-PL Configuration and expand the HP Slave AXI Interface. All write data beats for one write transaction are output before any write data beat for the next write transaction. Write interleave depth is a characteristic of the slave or the slave interface, rather than the master. rototyping by. By continuing to use our site, you consent to our cookies. amba 3. 1) IP核。 设置Memory Depth 为262144。 BRAM Instance 选择. 1. 2. mem, and CPI for CXL. The order within a single burst is maintained The order of first data needs to be the same with that of request Write Interleave Cability The maximum number of transactions that master can interleave ADDRESS A11 A21 A31. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. e. and interleaved read data completion of the transactions. AXI and AXI lite master. ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ ᅠ Select Download Format Axi Bus Protocol Ppt Slideshare Download Axi Bus Protocol Ppt Slideshare PDF Download Axi Bus Protocol Ppt Slideshare DOC ᅠ Commands to handle the interfaces that have been achieved at axi. For Design specification and Verification plan, refer to Memory Model. it seems that my waveform does not meet the axi spec, because the awready can not always be 1 in rtl. ----- We have C0/C1/C2/C3 linearly and consecutively addressed. Write Data Interleaving in AXI3 Slaves: With Write Data Interleaving, an AXI3 slave can accept interleaved write-data with different AWID values. 1) I would like to know how read and write address requests issued to slave are associated with read or write data. Read now: data analyst course in hyderabad. The AXI protocol enables: address information to be issued ahead of the actual data transfer support for multiple. Where interleaving is supported, the WID and RID signals will indicate which of the interleaved transactions the data transfer relates to. 1. But at the same time your write strobes are 0xFFFF thus all 16 byte lines are active. 2. 0 AXI Spec. Documentation and usage examples. QoS, Write Data Interleaving, unaligned data transfer, byte invariance. Bufferable AXI. AXI uses well defined master and slave interfaces that communicate via five different channels: Read address; Read data; Write address; Write data; Write response; Figure 1 shows the five AXI channels. Submit the transaction. 0 AXI out-of order - WID & RID - Architectures and Processors forum - Support forums - Arm Community - AXI terminology - Multiple outstanding , out of order , interleavingAMBA AXI and ACE Protocol Specification Version E. The controller provides the Read Data back to the user interface after issuing the READ command to the HBM2 DRAM. Implement build_phase and create a TLM analysis export instance. That is not allowed with the addresses of 1,2,3. View AXI Notes. The controller will run up to 2400Mbps in UltraScale and 2667Mbps in UltraScale+. Hi, I am trying to use DDR4 SDRAM ( MIG 2. sv","contentType":"file"},{"name":"axi. I have including seen many IP providers e. When accessing a slave that supports write data interleaving, write data from different transactions that use the same AWID cannot be interleaved. To avoid a deadlock situation, a slave interface must have a write interleaving depth greater than one only if it can continuously accept. PCIe AXI master module. DataMover AXI4 Write. posiible to achieve required through put as before using this sysytem? Any replies will be greatly appreciated. v. D14Supports AXI Master, AXI Slave, AXI Interconnect; Supports all ARM AMBA AXI 3. 0 interconnect. 1 it said that Write data channel information is always treated as buffered, so that the master can perform write transactions without slave acknowledgement of previous write transactions. The DQ bits are bi-directional and have a bus turnaround time associated when switching direction. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. The primary reason for removing WID was NOT to reduce the interface pin count, it was imply that the WID signal was no longer needed. m. However, the word of the data interleaving is not included in the AXI specifications but the write interleaving only exists. >In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave? First of all, an AXI4 master must not issue interleaved write data. It can be used to terminate device-to-device DMA operations with reasonable performance. On an AXI bus, IDs indicates the correspondence between addresses and data. addressing space for any slave on AXI bus interconnect. When accessing a slave that supports write data interleaving, write data from different transactions that use the same AWID cannot be interleaved. This site uses cookies to store information on your computer. But at the same time your write strobes are 0xFFFF thus all 16 byte lines are active. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition Description: Workaround: Status. 1中，调用AXI BRAM Controller (4. AxUSER, WUSER, RUSER, BUSER. b). Simran Sarai. 0 2 PG059 March 20, 2013…function int. The AxiMaster and AxiLiteMaster classes implement AXI masters and are capable of generating read and write operations against AXI slaves. " Thanks in advance, Amaresh There is no write data interleaving in AXI4. 0 AXI. If yours DUT supports more than only simple write then you have to add other signals. wstrb { Write strobes, his signal indicates which byte lanes to update in memory3 As per the standards, 4KB is the minm. LogiCORE IP AXI Interconnect v2. The primary reason for removing WID was NOT to reduce the interface pin count, it was imply that the WID signal was no longer needed. Typically, the read-modify-write operation can be achieved with a single atomic operation. Pass condition: If trace_tag is set to. AXI Interconnect v21 LogiCORE IP Product Guide Vivado Design Suite PG059 April 6 2016 AXI Interconnect Product Guide v21 2 PG059 April 6 2016 Table of Contents…Gaming, Graphics, and VR. Wait states are used if the buffer is full, or has less than 128 bytes of available space. The AMBA AXI-4 Master is designed in this project, which is modeled in Verilog and simulation results for read/write operation for data/address are shown in VCS tool. All rights. It connects one DDR4 device and two interleaved LPDDR4 devices, which requires one NoC instance to configure the DDRMC for the DDR4 device and another NoC instance to configure the two interleaved DDRMCs. Most AXI3 masters do not support write interleaving. Ensure that All Inputs and All Outputs are both unchecked. I'm interested to know what happens if on an AXI write transaction, the WR data channel put the channel info before the address channel info is valid. Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from the start of valid high? Explain AXI read transaction What is the AXI capability of data interleaving? Explain out-of-order transaction support on AXI? Explain multiple outstanding address pending?Interleaving codewords is an important method not only for combatting burst errors, but also for distributed data retrieval. {"payload":{"allShortcutsEnabled":false,"fileTree":{"AXI_Protocol/Design and Verification":{"items":[{"name":"AXI_Interface. value on the address channel. here is the part axi slave rtl generated by vivado. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one. // Documentation Portal . PG059-AXI-InTERconnEcT 编辑者： 时 间：2014-12-16 Introduction介绍 Xilinx LogiccoRE IP AXI In. Transaction ID信号，使AXI4协议可以完成自身的乱序机制，从AXI3到AXI4的进化中，write interleaving被取消了，大的方向下，AXI遵循着相同ID顺序执行，不同ID乱序执行的原则，同时从主设备-互联网络-从设备的连接中，Transaction ID可能会出现额外的位扩展. • AXI4-Lite does not support data interleaving, the burst length is defined as 1 • AXI4-Lite supports multiple. It converts 64-b it AXI transactions in to appropriate 32-bit. Allows reads to bypass writes, in contrast to axi_to_mem, however needs more hardware. You can also instantiate the AXI Data Width Converter core directly in your design (without AXI Interconnect core) along any pathway between a wide AXI master device and a narrower AXI slave. • Support for Read-only and Write-only masters and slaves, resulting in reduced resource utilization. Synopsys supporting burst lengths up to 256 beats at AXI3. Interleaving Options Non-interleaved Bank Interleave Without Chip Select Interleave Bank Interleave with Chip Select Interleave 12. 0 AXI. Decoder decodes the addresses received by master and goes to particular location of slave. Enables sharing the AXI CDMA module between multiple request sources, interleaving requests and distributing responses. g. >In AXI4 multi-master case how/where can i control 2 masters which are trying to access a single slave? First of all, an AXI4 master must not issue interleaved write data. State why you are writing (i. #- Program AXI3 Master VIP to drive a sequence of write transactions with write data interleaving. As a result, AXI4 removed support for write data interleaving, which then removed the need for the WID signal (it was only needed to work out which outstanding write transaction the data related to). By continuing to use our site, you consent to our cookies. 3. Where interleaving is supported, the WID and RID signals will indicate which of the interleaved transactions the data transfer relates to. Introduction to High Bandwidth Memory 3. 4 Write interleaving. "AXI3 supports write interleaving. Word count register – It contains the. Data interleaving, however, is not supported. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one. Data interleaving, however, is not supported. 5 Write data interleaving] "The order in which a slave receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec. Connected to axi bus ppt slideshareconfigured as AXI3 write data with interleaving (with write interleaving depth >1). • The data transfers for a sequence of write transactions with the same AWID value must complete in the order in which the master issued the addresses, see Normal write ordering and AXI3 write data interleaving on page A5-79. a. For example if you would like to test read operation then you also have to add all signals. Arbiter avoids the collision, when two masters initiate the transaction at a same time. A master interface that is. interleaving. Customize the AXI GPIO IP block:. The AMBA AXI4 Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. Chapter 2 Signal Descriptions Refer to this chapter for definitions of the AXI global, write address channel, write data channel, write response channel, read address channel, read data channel, and low-power interface signals. The problem I am facing is in AXI interface of MIG where 4-bit ID signal is present for all the transacti AXI-4 questions. The AMBA AXI protocol supports high-performance, high-frequency system designs. AXI3 carries locked transfers, AXI4 does NON support locked transfers. Figure 2-19: AXI Reference Guide UG761 (v13. scala . AXI-Pack achieves near-ideal peak on-chip bus utilizations of 87% and 39%, speedups of 5. cache or the AMBA CXS-B protocol specification. Write interleaving 1 2 1 Write interleaving depth = 1 X Write interleaving depth > 1 OK A B. transfer. Serial AXI Links in Broadcom System-on-Chip. I am pretty new to AMBA protocol and I am specifically interested in AXI-4. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one. Provides the blended video/audio to the PL via native video output or streaming AXI. In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) at axi slave model, then the data can be sent as following. g. DATA. In AXI spec 1. AMBA AXI Protocol Specification · AMBA AXI Protocol Specification. Activity points. apb_test doesn't extend from uvm_test. Chapter 4 Transfer Interleaving and Ordering Read this for a description of the stream interleaving and ordering restrictions. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When. This means the WID is not supported in AXI4. 17. AXI4 supports QoS, AXI3 does NOT suppor QoS. AXI4 to memory protocol (req, gnt, rvalid) converter. 2 v6 ) in Vivado IP Integrator. 3. sv","path":"src/axi_atop_filter. Tune for performance and re-simulate: Ensure that you have the right number of NoC NMUs and DDRMCs to meet your requirements. Stage 3: Write Calibration Part Two—DQ/DQS Centering 1. It is a Technique that divides memory into. Newest. [AXI spec - Chapter 8. The Write data interleaving of AXI protocol specification says: "A master interface that is capable of generating write data with only one AWID value generates all write data in. uitable for. 0 and v2. Enabling the Debug Report x. See the tests directory, verilog-axi, and verilog-axis for complete testbenches using these modules. 4. Prefix AW Denotes AXI write address channel signals. See the section in the AXI protocol titled "Dependencies between channel handshake signals . That is not allowed with the addresses of 1,2,3. 0 AXI. Interleaving as a study method means learning more than one subject or skill and switching between them. 4. 1 Answer. A locked transaction is changed to a non-locked transaction and propagated by the MI. Everything runs fine, the Linux application can start the VDHL AXI master to. This approach makes good use of memory. The DDRMC is a dual channel design with fine interleaving disabled. AXI3 master devices must be configured as if connected to a slave with a Write interleaving depth of one. AXI的读写事务可以通过ID来进行区分，从而引入顺序的概念。. Multiple Intellectual Property (IPs) are integrated in a single SoC and these IPs communicate with the help of various bus protocols. 1) A1 A2 B1 B2 (In-order)-> This is legal. pdf". If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. Appendix B Revisions This site uses cookies to store information on your computer. AXI3 supports write interleaving. scala . SIMON FRASER UNIVERSITY. Spring. 4. The slave declares a write data interleaving depth that indicates if the interface can accept interleaved write data from sources with different AWID values. In fact in AXI4 and for that matter in AXI5, the WID signals can be completely ignored. Develop and analyze applications with graphics and gaming tools, guides, and training for games developers. svt_axi_transaction:: get_byte_count. Hi, can you please explain what is interleaving, 1. 35 Chapter 2: AXI Support in Xilinx Tools and IPThe AMBA AXI-4 Master is designed in this project, which is modeled in Verilog and simulation results for read/write operation for data/address are shown in VCS tool. 深入理解AMBA总线（十一）AXI协议导论. Provides test pattern generator as replacement to one of the 2 rendering sources on stream1. Separate read, write and snoop channelsInterleaving simply means breaking a single transmission unit up into smaller pieces, and spreading those pieces out in time by sequencing them with pieces from other transmission units. 4. The HBM2 controller asserts the Read data in clock cycle TB. 9. p. 6 on the left. privileged transaction 6. For example, if you were learning multiplication, you might benefit from interleaving your multiplication practice with. txt) or read online for free. 1. I have seen many IP providers e. FIG. The AMBA AXI protocol supports high-performance, high-frequency system designs. Read now: data analyst course in hyderabad. A rather significant change seems to be the banning of write interleaving, which could help improve the system throughput. import all of my_pkg into your testbench. With reorder depth / interleaving depth of 1, everything has to be in-order regardless of IDs. Insert image from. Interleaving is a step on from this. The AXI interfaces conform to the AMBA® AXI version 4 specifications from ARM®, including the AXI4-Lite control register. AXI3 masterFigure 3 shows a timing diagram of an AXI write transaction. v : AXI central DMA engine rtl/axi_cdma_desc_mux. In case if we have 2 burst transfers with A (awid=0,wlen=2), B(awid=1,wlen=2) at axi slave model, then the data can be sent as following. 4. between master and slave using a write data channel to the slave or a read data channel to the master. . When YUV, it has to write in the order: Cr Y Cb; Support frame buffer formats, including 1,2,4,8,16,24, and 32 bits per pixel. • separate read and write data channels, that can provide low-cost Direct Memory Access (DMA)I change the hardware in EDK and then run the memory writing code in SDK and check if the data I write is being written to memory with delay or not. point to point) scheme. dfblob:120001dbc4d dfblob:c39f478f34a. IP Facts. Parametrizable interface width and. The problem is with your combination of the write address and the write strobes. For each write or read, start_delay AXI cycles are introduced after each command before the next write or read is issued. For example, a slave with a write data interleaving depth of two that has four different addresses, all with different AWID values, pending can accept data for either of the first. The AXI data interface consists of the following channels, which communicate with the Avalon® -ST interface through the AXI to. Read-only and Write-only variations are possible. AXI3: Write data interleaving (for different IDs) is supported. Secondly, the interconnect must ensure that. AXI specification says that the write data interleaving depth is statically configured and the slave declares a write data interleaving depth. but i got two questions about AXI after hi. Appendix B RevisionsAs stated in AXI3 write data interleaving on page A5-81, AXI4 removes support for write data interleaving. No. WID is needed to support write data interleaving described in AXI3, but this isn't supported in AXI4, so no requirement to have a WID signal. This covergroup is hit when address phase completion of four transactions are observed in a specific combination as described above. Check description: Trace tag value on data channel or resposne channel should be valid as per the trace tag. Stage 2: Write Calibration Part One 1. We would like to show you a description here but the site won’t allow us. As AXI provides many features such as out of order completion, interleaving; interconnect is responsible to take care of interleaving and out of order. • AXI4 Quality of Service (QoS) signals do not influence arbitration priority in AXI Crossbar. I think data interleaving should not be done within a single burst. Secondly, the interconnect must ensure that. the AXI3 spec described the following (seen in all AXI spec releases up to and including version F). The authors analysed the performance impact of the factors in a. There is one write strobe bit for every eight bits of write data. Besides Cortex-A9 master there are the other masters (DMAC, PL AXI masters) and there are AXI interconnects, that are at the same time slaves and masters, and passes write data from multiple sources (slave interfaces), and might interleve them. Write interleaving is hardly used by regular masters but can be used by fabrics that. Chapter 4 Transfer Interleaving and Ordering Read this for a description of the stream interleaving and ordering restrictions. Data packets of a maximum of 2 K bytes can be created. AHB supports the locked transfer. In practice, removing write interleaving from this part of the AMBA standard makes certain aspects of the AXI protocol easier to handle. Axi handshake. The AMBA AXI-4 system consists. In the case illustrated in. Stage 4: Read Calibration Part Two—Read Latency Minimization 1. - Write interleaving. The user logic should provide a valid write address in the AWADDR bus and assert the AWVALID to indicate that the address is valid. out of order* 4. 1. WID is removed in AXI4, so WDATA must strictly follow the AW order. The AXI4-Lite Cross-bar interconnect is used to connect one or more AXI4-Lite compliant master devices to one or more AXI4-Lite compliant slave devices. [Chapter 8.